Wiring patterns on a circuit board are formed to have various sizes and shapes. In order to test whether each of the wiring patterns is formed to have a desired shape and the like, a test is conducted as to whether the wiring pattern is formed in a favorable state by calculating a resistance value between predetermined two points (a continuity test) or calculating an insulation property between predetermined two points (an insulation test).
A conventional approach for testing a plurality of wiring patterns to be tested is a continuity test that involves defining desired sites, which are electrically connected to wiring patterns, on a surface of a circuit board as test points, and sending an electric signal between the desired test points, thereby testing for electrical continuity between the test points on the wiring pattern.
Moreover, a conventional typical approach for testing an insulation state between a first wiring pattern and a second wiring pattern is an insulation test that involves sending an electric signal to a test point on a first wiring pattern, and measuring an electric signal detected from a test point on a second wiring pattern, thereby testing insulation state between the wiring patterns.
In particular, wiring patterns on a circuit board are formed more finely and have become more complicated with recent miniaturization of such circuit boards. Moreover, the wiring patterns are formed with narrower pitches. As a result, the manufacturing process tends to become more complicated. Therefore, an insulation failure which cannot be found by a conventional insulation test is a problem. In order to solve the problem in the prior art, a test is conducted by changing a value of voltage applied to or current fed to a wiring pattern in a stepwise manner so as to prevent an insulation failure portion and the like of the wiring pattern from being burned down by overcurrent (see, JP 6-230058A).
The applicant has proposed a circuit board testing method capable of finding the existence of an insulation failure including a pseudo short-circuit portion where adjacent wiring patterns are short-circuited in a pseudo manner (see, JP 2008-139036A).
However, while the insulation test methods disclosed in Patent Literature 1 or 2 are capable of finding an insulation failure or a pseudo insulation failure between wiring patterns, they are incapable of calculating an accurate resistance value for the failure.
Heretofore, circuit boards with a short-circuit failure have been usually discarded. However, the probability that such a failure occurs has increased because the wiring patterns are formed to have narrower line widths and pitch widths as described above. As a result, the higher defective rate adversely affects circuit board manufacturing costs. Circuit board manufacturers have a significant challenge to reduce the defect rate caused by such failure and analyzing the failure is an important factor.